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MC74VHC244 Octal Bus Buffer
The MC74VHC244 is an advanced high speed CMOS octal bus buffer fabricated with silicon gate CMOS technology. The MC74VHC244 is a noninverting 3-state buffer, and has two active-low output enables. This device is designed to be used with 3-state memory address drivers, etc. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7 V, allowing the interface of 5 V systems to 3 V systems. * High Speed: tPD = 3.9 ns (Typ) at VCC = 5 V * Low Power Dissipation: ICC = 4 mA (Max) at TA = 25C * High Noise Immunity: VNIH = VNIL = 28% VCC * Power Down Protection Provided on Inputs * Balanced Propagation Delays * Designed for 2 V to 5.5 V Operating Range * Low Noise: VOLP = 0.9 V (Max) * Pin and Function Compatible with Other Standard Logic Families * Latchup Performance Exceeds 300 mA * ESD Performance: Human Body Model > 2000 V Machine Model > 200 V * Chip Complexity: 136 FETs * Pb--Free Packages are Available*
2 4 6 8 11 13 15 17 18 16 14 12 9 7 5 3
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20
20 1
VHC244 AWLYYWWG 1
SOIC-20 WB DW SUFFIX CASE 751D
20
20 1
VHC 244 ALYW 1
TSSOP-20 DT SUFFIX CASE 948E
20
20 1
74VHC244 AWLYWW 1
A1 A2 A3 A4 B1 B2 B3 B4
YA1 YA2 YA3 YA4 YB1 YB2 YB3 YB4 NONINVERTING OUTPUTS
SOIC EIAJ-20 M SUFFIX CASE 967 A WL, L YY, Y WW, W
= Assembly Location = Wafer Lot = Year = Work Week
DATA INPUTS
PIN ASSIGNMENT
OEA A1 YB4 A2 YB3 A3 YB2 A4 YB1 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC OEB YA1 B4 YA2 B3 YA3 B2 YA4 B1
OUTPUT ENABLES
1 OEA 19 OEB
Figure 1. Logic Diagram
*For additional information on our Pb--Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
ORDERING INFORMATION
See detailed ordering and shipping information in the Ordering Information Table on page 2 of this data sheet.
March, 2006 - Rev. 7 -
1
Publication Order Number: MC74VHC244/D
MC74VHC244
FUNCTION TABLE
INPUTS OEA, OEB L L H A, B L H X OUTPUTS YA, YB L H Z
ORDERING INFORMATION
Device MC74VHC244DW -- OBSOLETE* MC74VHC244DWR2 MC74VHC244DT MC74VHC244DTR2 MC74VHC244M -- OBSOLETE* MC74VHC244MEL Package SOIC--20 WB SOIC--20 WB TSSOP--20 (Pb--Free) TSSOP--20 (Pb--Free) SOIC EIAJ--20 (Pb--Free) SOIC EIAJ--20 (Pb--Free) Shipping 38 Units/Rail 1000/Tape & Reel 75 Units/Rail 2500/Tape & Reel 1600 Units/Box 2000/Tape & Reel
*This device is obsolete, information available for reference. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
MAXIMUM RATINGS (Note 1)
Symbol VCC VIN VOUT IIK IOK IOUT ICC PD TSTG VESD Positive DC Supply Voltage Digital Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Storage Temperature Range ESD Withstand Voltage Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) Above VCC and Below GND at 125C (Note 5) SOIC TSSOP SOIC TSSOP Parameter Value --0.5 to +7.0 --0.5 to +7.0 --0.5 to VCC +0.5 --20 20 25 75 500 450 --65 to +150 >2000 >200 >2000 300 96 128 Unit V V V mA mA mA mA mW C V
ILATCHUP JA
Latchup Performance
mA C/W
Thermal Resistance, Junction--to--Ambient
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2. Tested to EIA/JESD22--A114--A 3. Tested to EIA/JESD22--A115--A 4. Tested to JESD22--C101--A 5. Tested to EIA/JESD78
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MC74VHC244
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN VOUT TA tr, tf DC Supply Voltage DC Input Voltage DC Output Voltage Operating Temperature Range, all Package Types Input Rise or Fall Time VCC = 3.3 V + 0.3 V VCC = 5.0 V + 0.5 V Characteristics Min 2.0 0 0 --55 0 Max 5.5 5.5 VCC 125 100 20 Unit V V V C ns/V
DEVICE JUNCTION TEMPERATURE VERSUS TIME TO 0.1% BOND FAILURES
Time, Hours 1,032,200 419,300 178,700 79,600 37,000 17,800 8,900 Time, Years 117.8 47.9 20.4 9.4 4.2 2.0 1.0 NORMALIZED FAILURE RATE Junction Temperature C 80 90 100 110 120 130 140 FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = 130 C TJ = 120 C TJ = 110 C TJ = 100 C TJ = 80 C 100 TIME, YEARS TJ = 90 C
1 1 10 1000
Figure 2. Failure Rate vs. Time Junction Temperature
DC CHARACTERISTICS (Voltages Referenced to GND)
VCC Symbol VIH Parameter Minimum High--Level Input Voltage Maximum Low--Level Input Voltage Maximum High--Level Output Voltage VIN = VIH or VIL IOH = --50 mA VIN = VIH or VIL IOH = --4 mA IOH = --8 mA VOL Maximum Low--Level Output Voltage VIN = VIH or VIL IOL = 50 mA VIN = VIH or VIL IOH = 4 mA IOH = 8 mA IIN IOZ ICC Input Leakage Current Maximum 3--State Leakage Current Maximum Quiescent Supply Current (per package) VIN = 5.5 V or GND VIN = VIH or VIL VOUT = VCC or GND VIN = VCC or GND 5.5 4.0 40.0 40.0 mA Condition (V) 2.0 3.0 to 5.5 2.0 3.0 to 5.5 2.0 3.0 4.5 3.0 4.5 2.0 3.0 4.5 3.0 4.5 0 to 5.5 5.5 1.9 2.9 4.4 2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 0.1 0.25 2.0 3.0 4.5 Min 1.5 VCCX 0.7 0.5 VCCX 0.3 1.9 2.9 4.4 2.48 3.8 0.1 0.1 0.1 0.44 0.44 1.0 2.5 TA = 25C Typ Max TA 85C Min 1.5 VCCX 0.7 Max 1.5 VCCX 0.7 0.5 VCCX 0.3 1.9 2.9 4.4 2.34 3.66 0.1 0.1 0.1 0.52 0.52 1.0 2.5 mA mA V -55C TA 125C Min 1.5 VCCX 0.7 0.5 VCCX 0.3 V V Max Unit V
VIL
VOH
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MC74VHC244
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
TA = 25C Symbol tPLH, tPHL Parameter Maximum Propagation Delay, A to YA or B to YB Test Conditions VCC = 3.3 0.3 V VCC = 5.0 0.5 V VCC = 3.3 0.3 V RL = 1 k VCC = 5.0 0.5 V RL = 1 k VCC = 3.3 0.3 V RL = 1 k VCC = 5.0 0.5 V RL = 1 k VCC = 3.3 0.3 V (Note 6) VCC = 5.0 0.5 V (Note 6) Cin Cout Maximum Input Capacitance Maximum Three--State Output Capacitance (Output in High--Impedance State) CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF 4 6 Min Typ 5.8 8.3 3.9 5.4 6.6 9.1 4.7 6.2 10.3 6.7 Max 8.4 11.9 5.5 7.5 10.6 14.1 7.3 9.3 14.0 9.2 1.5 1.0 10 TA 85C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 10.0 13.5 6.5 8.5 12.5 16.0 8.5 10.5 16.0 10.5 1.5 1.0 10 -55C TA 125C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 11.0 14.5 7.5 9.5 13.5 17.0 9.5 11.5 17.0 11.5 1.5 1.5 10 pF pF ns ns ns Unit ns
tPZL, tPZH
Output Enable Time OEA to YA or OEB to YB
tPLZ, tPHZ
Output Disable Time OEA to YA or OEB to YB
tOSLH, tOSHL
Output to Output Skew
Typical @ 25C, VCC = 5.0V CPD Power Dissipation Capacitance (Note 7) 19 pF 6. Parameter guaranteed by design. tOSLH = |tPLHm -- tPLHn|, tOSHL = |tPHLm -- tPHLn|. 7. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC/8 (per bit). CPD is used to determine the no--load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V)
TA = 25C Symbol VOLP VOLV VIHD VILD Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage Parameter Typ 0.6 --0.6 Max 0.9 --0.9 3.5 1.5 Unit V V V V
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MC74VHC244
SWITCHING WAVEFORMS
VCC 50% tPLH YA or YB 50% VCC tPHL GND YA or YB YA or YB VCC tPZL 50% VCC tPZH 50% VCC tPHZ tPLZ GND HIGH IMPEDANCE VOL +0.3V VOH --0.3V HIGH IMPEDANCE
A or B
OEA or OEB
50%
Figure 3. Switching Waveform
Figure 4. Switching Waveform
TEST CIRCUITS
TEST POINT OUTPUT DEVICE UNDER TEST CL* DEVICE UNDER TEST
TEST POINT OUTPUT 1 k CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
CL*
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 5. Test Circuit
Figure 6. Test Circuit
INPUT
Figure 7. Input Equivalent Circuit
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MC74VHC244
OUTLINE DIMENSIONS
SOIC-20 WB DW SUFFIX CASE 751D--05 ISSUE G
D
A
11 X 45 _
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1 10
20X
B 0.25
M
B TA
S
B
S
A e
SEATING PLANE
h
18X
A1
T
C
TSSOP-20 DT SUFFIX CASE 948E--02 ISSUE B
20X
K REF
M
L
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
2X
L/2
20
11
K K1 B J J1 SECTION N-N
L
PIN 1 IDENT 1 10
--U-
N 0.15 (0.006) T U
S
0.25 (0.010) M
A --VN F
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE --W--. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 -----1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 -----0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
DETAIL E C D 0.100 (0.004) - - SEATING -TPLANE
--WG
H
DETAIL E
DIM A B C D F G H J J1 K K1 L M
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MC74VHC244
OUTLINE DIMENSIONS
SOIC EIAJ-20 M SUFFIX CASE 967--01 ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX -----2.05 0.05 0.20 0.35 0.50 0.18 0.27 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 -----0.81 INCHES MIN MAX -----0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 -----0.032
20
11
LE Q1 M_ L DETAIL P
E HE
1
10
Z D e A VIEW P
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC74VHC244
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PUBLICATION ORDERING INFORMATION
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MC74VHC244/D

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